Solid state traveling display circuit

ABSTRACT

A plurality of solid state display cells, individually including a light-emitting element and a memory element, are connected in tandem via transfer circuitry to provide a traveling display image. The transfer circuitry interconnects the memory elements of adjacent display cells and operates in conjunction with an AC bias voltage applied in common to the display cells for moving the display image through successive display cells.

United States Patent Ngo [ 51 Mar. 21, 1972 SOLID STATE TRAVELING DISPLAY CIRCUIT Dinh-Tuan Ngo, Colts Neck, NJ.

Bell Telephone Laboratories, Incorporated, Murray Hill, NJ.

Nov. 20, 1969 Inventor:

Assignee:

Filed:

Appl. No.:

[1.8. CI. ..340/l73 R Int. Cl ..G09b 13/00, H05!) 39/00 Field of Search ..340/l73 R, 173 LT, 324 R, 334,

References Cited UNITED STATES PATENTS Clark ..307/250 X 3,389,389 6/1968 Minear ..340/339 3,432,846 3/1969 Jones et a]. ....340/339 3,440,489 4/1969 Davidson et al. ....307/249 X 3,493,957 2/1970 Brooks ....340/334 X Primary Examiner-Maynard R. Wilbur Assistant Examiner-Jeremiah Glassman Attorney-R. J. Guenther and Kenneth B. Hamlin [57] ABSTRACT 13 Claims, Drawing Figures CO(IEJ(lZ'1BO LH WRITE- ERASE cmcumw T ,7: 72 o I Y i r I f I 92 91 AC. SOURCE I CELL DRIVER 72 l E 941 42 I IELECTRO- Q S I 4 I T LUMINESCENT \80 0 moms us A g c4 ew 1 I 1 CL |E A R Z l I I 33 LT I i l l 4 11 m n SHEET lb [1F 4 FIG. 6

CONTROL CCT. 2

.2 2 IQ K 7 m .60 T6 C. 6 C \66 L 94 .31.. E 9 K t||l E .C CR Am 3 ERASE PULSE TRANSFER PULSE FIG. 7B

VOLTAGE ACROSS STORAGE ELEMENT SOLID STATE TRAVELING DISPLAY CIRCUIT BACKGROUND OF THE INVENTION This invention relates to display systems and, more particularly, to display systems upon which traveling or moving images are generated by the selective energization and deenergization of independent display cells or elements.

Display systems are used typically for generating patterns of information, or images, in a two-dimensional raster for information display media, computer input/output terminals, telemetered data and the like. The principal types of display systems currently available include matrix arrangements of light bulbs or neon tubes and various forms of cathode ray tube presentations, all of which suffer from well-known disadvantages related to size, cost, ruggedness and power requirements. Further, to provide for travel or movement of the image across the display field, in the manner of the so-called Times Square type display," known systems have employed electromechanical switching arrangements or complex and expensive electronic control circuitry. The need for a display system which would overcome these disadvantages has been apparent for some time.

Solid state semiconductor displays currently show considerable promise for eliminating or minimizing many of the disadvantages of earlier display systems. Thus, for example, solid state semiconductor displays eliminate the need for high operating voltages and are compatible with semiconductor switching circuitry. However, generally they suffer from certain limitations in that they require external memory storage and associated circuitry to regenerate the display image. Moreover, known solid state semiconductor displays still require rather complex and expensive control circuitry for providing a traveling display image. This substantially increases the cost and complexity of such solid state display systems.

SUMMARY OF THE INVENTION It is accordingly a general object of this invention to provide a new and improved arrangement for displaying traveling patterns of information without the disadvantages of known display arrangements.

More particularly, it is an object of this invention to provide a solid state semiconductor traveling display arrangement which simplifies the control circuitryrequired for image regeneration and movement.

The above and other objects are attained in a simple and economical manner in an illustrative embodiment of a traveling display circuit according to my invention comprising an array of display cells, each cell including the serially-connected combination of a light-emitting element such as an electroluminescent diode, a charge storage element and a bilateral switching element. The bilateral switching element and the charge storage element provide inherent memory for the display cell, operating in conjunction with an alternating current bias voltage to maintain the cell diode lighted upon application of a write pulse.

In operation, the alternating current bias voltage is continuously applied across each display cell of the array. A particular cell can be turned ON, i.e., lighted, by a write pulse applied to the particular cell, the write pulse being sufficient to operate the cell bilateral switching element to a conducting state. The resulting current flow charges the cell storage element and energizes the electroluminescent diode for light emission. During succeeding half-cycles of the bias voltage the stored charge, in combination with the bias voltage, causes periodic operation of the bilateral switching element to permit sufficient current flow to maintain the electroluminescent diode lighted. The display cell can be turned OFF by an erase pulse applied to the cell to operate the bilateral switching element to a conducting state at a time when the bias voltage is at or near zero, thereby removing the charge from the storage element and preventing the recharging thereof.

In accordance with one aspect of the present invention for providing a traveling display image, the erase pulse is applied to the cell advantageously at a time when the bias voltage is not at or near zero, such that a residual charge is left on the cell charge storage element. The residual charge is extended to the succeeding display cell in the array and is sufficient, in combination with a successive transfer pulse, to operate the succeeding cell bilateral switching element to a conducting state. The resulting current flow charges the succeeding cell storage element and energizes the electroluminescent diode thereof for light emission. The transfer pulse is applied in common to all cells of the display array but is insufficient to operate a cell bilateral switching element to a conducting state in the absence of residual charge extended thereto from the preceding cell. Thus, by alternately applying erase and transfer pulses in common to each cell of the display at a desired traveling frequency, the display image is moved through successive cells of the array.

According to another embodiment of the invention, intermediate storage elements are provided between adjacent display cells, and cycles of three successive pulses are employed for effecting a traveling display image. In conjunction with the bias voltage, the first pulse transfers the display information to the intermediate storage elements, the second pulse erases all display cells, and the third pulse transfers the display information from the intermediate storage elements to the succeeding display cells. Continuously operating clear circuitry connected in common to the intermediate storage elements clears the intermediate storage elements following transfer of the display information therefrom.

A traveling display circuit in accordance with my invention is compact, rugged and reliable and is inexpensive to manufacture, being susceptible to integrated circuit manufacturing techniques. Further, it has low operating power requirements,

simple addressing circuit requirements and may be operated directly by high speed digital signals of the amplitude generated by integrated circuits, thereby eliminating the need for interface or buffer circuitry.

BRIEF DESCRIPTION OF THE DRAWING The above and other objects and features of the invention may be fully apprehended from the following detailed description and the accompanying drawing, in which:

FIG. I is a diagram of an illustrative embodiment of a solid state traveling display circuit in accordance with the principles of my invention;

FIGS. 2A, 2B and 2C are time charts useful in describing the operation of the illustrative embodiment of FIG. 1;

FIG. 3 depicts an alternative illustrative embodiment of a display cell for a traveling display circuit in accordance with the principles of my invention;

F IG. 4 depicts a typical voltage-current characteristic for an illustrative bilateral switching element employed in the embodiments of FIGS. 1 and 3;

FIG. 5 shows another illustrative embodiment of a traveling display circuit according to the principles of my invention, employing serial input of display information;

FIG. 6 shows a further illustrative embodiment of a traveling display circuit according to my invention; and

FIGS. 7A and 7B are time charts useful in describing the operation of the illustrative embodiment of FIG. 6.

DETAILED DESCRIPTION In FIG. 1 of the drawing, an illustrative embodiment of a traveling display circuit is shown comprising a portion of an array for generating images by the selective energization and deenergization of individual ones of a plurality of display cells. The array may be assumed, for the purposes of illustration, to comprise a coordinate row and column field of display cells upon which the display image is generated and moved at a desired traveling rate to the left or right along the rows of the array. Two adjacent display cells and in one row of the array are shown in FIG. 1 and are interconnected by transfer circuit 60 for movement of the display image, by way of example, from right to left in FIG. 1. It will be apparent from the description herein, however, that the display cells may be employed in any form of array desired for particular display system applications, with individual transfer circuits interconnecting adjacent display cells along the direction of image movement.

Each display cell of the array includes the serially-connected combination of a light-emitting element and a memory element extending between a particular row and column conductor, the memory element including a bilateral switch and a charge storage element. Thus, display cell 100 comprises light-emitting element 103 including electroluminescent diode 116, and memory element 101 including bilateral breakdown switch 112 and capacitor 113, connected between column conductor C4 and row conductor R2. Similarly, adjacent'display cell 120 comprises light-emitting element 123 including electroluminescent diode 136, and memory element 121 including bilateral breakdown switch 132 and capacitor 133, connected between column conductor C3 and row conductor R2. Electroluminescent diodes 1 l6 and 136 may, for example, be red light-emitting gallium-arsenide-phosphide diodes, green light-emitting gallium-phosphide diodes, infrared lightemitting gallium-arsenide diodes (particularly advantageous in terms of integrated circuit manufacture) or any other of the knowntypes of light-emitting diodes. Bilateral switches 112 and 132 may compromise, for example, silicon PNPN-bilateral breakdown switches, Ovonic threshold switches, or the like, having the typical voltage-current characteristic shown in FIG. 4.

Specifically referring to FIG. 4, when the magnitude of the voltage across switch 112 or 132 equals or exceeds the forward breakdown voltage V or the reverse breakdown voltage V which are typically of substantially like magnitude, the switch breaks down to a low impedance conducting state. The switch remains in the low impedance conducting state until the voltage thereacross falls below the sustaining voltage level V or V at which point the switch returns to its quiescent high impedance nonconducting state. For an illustrative silicon PNPN bilateral switch, by way of example, the breakdown voltage may be on the order of :8 volts and the sustaining voltage level on the order of 10.5 volts.

Alternating current bias voltage provided by source 20, which may be either sinusoidal or pulsed, is extended by control circuit 80 across each display cell via the row and column conductors of the array. The bias voltage extended by source 20 across each cell is of a magnitude less than the breakdown voltage level for the bilateral switches, such as switches 112 and 132, but advantageously is greater than the sustaining voltage level therefor. Assuming use of the illustrative silicon PNPN-bilateral switches mentioned above, for example, the bias voltage provided by source 20 may be on the order of or 6 volts zero to peak with a frequency on the order of 10 kHz.,

' for example.

Addressing of a selected display cell is effected illustratively in FIG. 1 by application of coincident signals to the particular row and column conductors connected to the display cell under control of control circuit 80. The voltage thus extended across the selected display cell by the coincident row and column signals, in conjunction with the bias voltage applied to the row and column conductors, is sufficient to effect breakdown of the bilateral switch at the selected cell. At the same time, however, the voltage extended across the other display cells connected to the addressed row conductor and to the addressed column conductor is insufficient to effect breakdown of the bilateral switches at these other cells.

The addressing signals, as well as the bias voltage in the embodiment of FIG. 1, are applied to the row and column conductors of the array through respective row and column cell drivers, such as cell drivers 40 connected to column conductors C3 and C4 and cell driver 45 connected to row conductor R2, illustratively shown in FIG. 1 as pulse transformers. Thus,

source 20 is connected to each column conductor via the secondary winding 42 of a respective column cell driver 40 and to each row conductor via the secondary winding 47 of a respective row cell driver 45. The column conductors are addressed selectively by signals from write-erase circuitry on individual leads, such as lead 91 and 92, respectively connected to the primary windings 41 of respective column cell drivers 40. Similarly, the row conductors are addressed selectively by signals from write-erase circuitry 90'on individual leads, such as lead 95, respectively connected to primary windings 46 of respective row cell drivers 45.

Adjacent display cells in the direction of desired movement of the display image are interconnected via transfer circuits such as transfer circuit 60. Transfer circuit 60 includes a pair of transfer elements illustratively comprising transistors 65 and 67, and an intermediate storage element 63 depicted as a capacitor. Intermediate storage element 63 is connected between source 20 and a point between the output of the upstream transfer element transistor 67, and the input of the downstream transfer element, transistor 65. Storage element 63 is also connected through diode 62 over clear lead 50 to the output of clear circuit 30 in control circuit 80.

With the above description in mind, and with reference to FIGS. 2A, 2B and 2C, consider now the operation of the illustrative display circuit embodiment of FIG. 1. Assume initially that display cells and are OFF, i.e., that no charge appears on capacitors 113 and 133, that switches 112 and 132 are in high impedance nonconducting states, and that electroluminescent diodes 116 and 136 are thus not lighted. The

bias voltage from source 20 extended through the respective row and column cell drivers to row conductor R2 and column conductors C3 and C4 appears across each of display cells 100 and 120 as shown in FIG. 2A. Since the bias voltage is less than the breakdown voltage of switches 112 and 132, no significant current flow through display cells 100 and 120 occurs.

Assume now that it is desired to turn ON display cell 120 located at the intersection of row conductor R2 and column conductor C3; that is, assume that it is desired to register a bit of display information of one binary character, such as binary l, in display cell 120. This is accomplished by addressing row conductor R2 and column conductor C3 with coincident signals in the form of a write pulse which, in conjunction with the bias voltage applied across the display cell, is sufficient to effect breakdown of switch 132 and cell 120. In the manner described above, in the illustrative embodiment of FIG. 1 the write pulse is extended over row conductor R2 and column conductor C3 to display cell 120 via coincident signals applied on leads 95 and 91 from write-erase circuitry 90, which signals are reflected through the corresponding row and column cell drivers 45 and 40. Advantageously, to minimize the magnitude of the write pulse required, the write pulse is applied to the selected display cell under control of control circuit 80 near a peak of the bias voltage, as shown at time 1,, by way of example, in FIG. 2A.

The write pulse applied to row conductor R2 and column conductor C3 causes momentary breakdown of switch 132 at display cell 120, permitting current flow therethrough to register a charge on capacitor 133 and to energize electroluminescent diode 136. The resulting current flow through the display cell during breakdown of switch 132 is in the form of a current pulse, shown as pulse 201 in FIG. 2C, which may illustratively be on the order of 80 mA. magnitude with a duration on the order of several hundred nanoseconds.

The current flow through display cell 120 charges capacitor 133, as depicted in FIG. 28, to a level V determined principally by the net voltage across switch 132 during breakdown. During the following negative half-cycle of bias voltage applied across display cell 120, the charge on capacitor 133 adds to the bias voltage as shown in FIG. 2A. At time t,, the combined voltage exceeds the breakdown voltage V of switch 132, momentarily switching switch 132 to a low impedance conducting state. The resulting negative current pulse 202 through diode 134, connected in parallel with and poled opposite to electroluminescent diode 136, discharges capacitor 133 and charges capacitor 133 in a reverse direction, as indicated in FIG. 2B.

During the following positive half-cycle of bias voltage, the reverse charge on capacitor 133 adds to the bias voltage as shown in FIG. 2A, reaching a level sufficient to breakdown switch 132 again at time The positive current pulse 203 resulting therefrom through electroluminescent diode 136 reverses the charge on capacitor 133 and again energizes diode 136. During succeeding half-cycles of the bias voltage, the charge stored on capacitor 133, in combination with the bias voltage, causes periodic breakdown of switch 132 to permit sufficient current flow to maintain electroluminescent diode 136 lighted.

It will be noted, of course, that current flow through electroluminescent diode 136 occurs only during the positive current pulses, such as pulses 201 and 203 in FIG. 2C. Thus, diode 136 is advantageously energized for light-emission only briefly during each cycle of bias voltage from source 20. However, diode 136 appears to an observer to emit light continuously at a steady level during the period that the display cell is ON. Moreover, it will be apparent that diode 134 may also be a light-emitting electroluminescent diode if desired for a particular application, diode 134 being energized by the negative current pulses, such as pulses 202 and 204 in FIG. 2C.

An important advantage arises through the above-described current-pulsed energization of the electroluminescent diodes in the array. In particular, the operating power requirements are substantially lower, up to several orders of magnitude lower, than for known direct-current energized solid state display arrangements. Further, driving the electroluminescent diodes with high current pulses permits the diodes to be operated at or near maximum efficiency, thereby generally increasing the apparent brightness of the display image while reducing the power required.

Additional ones of the display cells in the array may be turned ON in a similar manner by application of a write pulse to the particular row and column conductors to which the additional cells are connected. Conversely, if desired, a selected display cell can be turned OFF by applying an erase pulse to the row and column conductors to which the selected cell is connected, such that the erase pulse removes or erases the charge stored at the selected CELL. Turning a display cell OFF corresponds to the registration in the display cell of a bit of display information of the other binary character, such as a binary O. This may be effected advantageously by applying an erase pulse to the particular row and column conductors of sufficient magnitude to break down the bilateral switch at a point in time when the instantaneous magnitude of the bias voltage applied to the row and column conductors is at or near zero. During the resulting momentary breakdown of the bilateral switch, therefore, no significant charge is stored on the charge storage element of the display cell. Accordingly, when the cell bilateral switch returns to its high impedance state, the net voltage across the display cell is approximately equal to the bias voltage and is thus insufficient to cause subsequent breakdown of the bilateral switch.

For example, assume that display cell 120 is ON and that it is desired to turn it OFF. Row conductor R2 and column conductor C3 are addressed via coincident signals applied on leads 95 and 91 in the form of an erase pulse at a time when the instantaneous value of the bias voltage is near zero, as shown at time 1,, by way of example, in FIG. 2A. The erase pulse is assumed to be sufficient in magnitude to cause momentary breakdown of switch 132 at display cell 120. The resulting current flow, depicted in FIG. 2C by current pulse 210, discharges charge storage element 133, as shown in FIG. 2B, and energizes electroluminescent diode 136. As mentioned above, since the instantaneous value of bias voltage across cell 120 at time t, is approximately zero, no significant charge builds up on capacitor 133 during the momentary breakdown of switch 132. As switch 132 returns to its high impedance nonconducting state, therefore, diode 136 is deenergized and remains so until capacitor 133 is again charged, such as upon application of a subsequent write pulse to cell 120.

Although in the description above, it is tacitly assumed that only a single display cell is addressed by a write or erase pulse during each cycle of the bias voltage, it will be apparent that more than one cell can be addressed during each bias voltage cycle by consecutively or concurrently addressing a number of cells in each cycle, for example, one column of display cells. Further, although a capacitor is illustratively depicted as the display cell charge storage element in the embodiment of FIG. 1, other types of charge storage elements, such as charge storage diodes, may be employed advantageously.

Assume at this point then that a bit of display information is registered in display cell 120, that is that display cell 120 is ON. Assume further that it is now desired to move the display information one column to the left, that is to move the display bit from cell 120 to cell 100. This is effected in FIG. I by the use of three successive pulses in conjunction with the bias voltage applied across the display cells, the first pulse transferring the display information to the intermediate storage elements, the second pulse erasing all display cells, and the third pulse transferring the display information from the intermediate storage elements to the succeeding display cells.

The first pulse is extended by control circuit over lead 71 to the upstream one of the transfer elements in each transfer circuit in the display array, such as transistor 67 in transfer circuit 60. This may occur, for example, at time t, in FIGS. 2A, 2B and 2C. At the same time, the voltage across capacitor 133 in display cell 120, depicted in FIG. 2B, is extended over lead 137 to the base of transistor 67. Consequently, intermediate storage element 63 is charged, illustratively in the positive direction to the voltage level across capacitor 133. Subsequently, at time 2,. in FIGS. 2A, 2B and 2C for example, a second or erase pulse is applied by control circuit 80 through write-erase circuitry to each display cell in the array to discharge the charge storage element thereat, such as capacitor 133 in display cell 120, in the manner described above. The voltage across capacitor 133 is thus returned to zero as shown in FIG. 2B.

The display image is accordingly registered briefly in the transfer circuit intermediate storage elements and all of the display cells in the array are turned OFF. At time t, in FIGS. 2A, 2B and 2C, the image is transferred to the succeeding display cell in the direction of desired image movement. Thus, at time 2,, a third pulse is extended by control circuit 80 over lead 72 to the downstream one of the transfer elements in each transfer circuit, such as transistor 65 in transfer circuit 60. At the same time, the voltage across intermediate storage element 63 is extended to the base of transistor 65, charging capacitor 113 in display cell to the voltage level across element 63.

The charge thus stored on capacitor 113, in conjunction with the bias voltage across display cell 100, is sufficient to turn ON display cell 100 when the bias voltage nears a peak such that the bias voltage added to the charge on capacitor 113 exceeds the breakdown voltage of bilateral switch 112. This may be, for example, at a time substantially coincident with, or shortly after, the transfer of the charge from intermediate storage element 63 to capacitor 113. The resulting breakdown of switch 112 permits current flow through cell 100, lighting electroluminescent diode 116 in the manner described above. During succeeding half-cycles of the bias voltage, periodic breakdown of switch 112 occurs to permit sufficient current flow to maintain diode 116 lighted until it is desired to move the display again one column to the left.

If a binary zero were originally registered in display cell 120, instead of the binary one assumed above, no charge would be stored on capacitor 133 at time I, when the first pulse appears on lead 71. Accordingly, the base of transistor 67 would be connected to the ground side of source 20 through capacitor 133 over row conductor R2 and lead 22. Transistor 67 would thus shunt the transfer pulse on lead 71 therethrough to potential source 68. No charge would be stored on intermediate storage element 63 during the appearance of the pulse on lead 71. When the third pulse appears on lead 72, therefore, the ground side of source 20 would be connected through element 63 to the base of transistor 65, and the pulse on lead 72 would be shunted through transistor 65 to potential source 69. Consequently, no charge would be stored on capacitor 113, thereby indicating a binary zero registered in cell 100.

Upon completion of movement of the display bits from one column of display cells to the next, the transfer circuit storage elements are cleared by the operation of clear circuit 30. Clear circuit 30 comprises a bilateral breakdown switch 31, capacitor 32 and impedance 33 serially connected across source 20. Impedance 33 may simply comprise a lightemitting element such as element 103, if desired, such that a display cell identical to those of the array can be used advantageously inclear circuit 30. Clear circuit 30 also includes a transistor 37, the base of which is connected to point 35 between impedance 33 and capacitor 32. The collector of transistor 37 is connected over clear lead 50 to each transfer circuit in the display array.

In operation, capacitor 32 is initially charged, such as by a write pulse in the manner described above for display cells in the array. Thereafter, the charge on capacitor 32 is reversed during succeeding half-cycles of the bias voltage similar to that shown for the ON period of a display cell in FIG. 2B. During the portion of each cycle of bias voltage that the potential of point 35 is positive, transistor 37 is switched to a conducting state, extending ground potential therethrough over lead 50 to each transfer circuit. This provides a path over which the intermediate storage elements in each transfer circuit, such as element 63 in transfer circuit 60, are discharged or cleared.

In many applications it is necessary to write information into only a small number of display cells, such as a single column of cells in the array. However, it is still necessary in these applications to erase the display information from all I display cells during movement of the display image. An alternative display cell embodiment is shown in FIG. 3 which ineludes a transistor switch for directly addressing the individual display cell for erase purposes, thereby eliminating the cell drivers of F 1G. 1 except where required for selective cell energization purposes. Thus, for example, if information is written into only a single column of the display array, it will be necessary to provide cell drivers only for the one column and for each row of the array.

Memory element 301 and light-emitting element 303 in the display cell embodiment of FIG. 3 may be substantially identical to elements 101 and 103, respectively, in FIG. 1. The display cell is addressed to erase or discharge the storage element thereof by extending an erase pulse from the control circuit over erase lead 311, which is connected in common to all display cells. At the display cell the erase pulse on lead 311 is extended to the base of transistor 310, switching transistor 310 to a conducting state. Charge storage element 313 is thus discharged, the path therefor being traced from storage element 313 over lead 315 through diode 343, transistor 310 and impedance 347 to ground potential.

In FIG. 5 an illustrative embodiment of a single input traveling display circuit is shown in which the display information is received in the form of a serial stream of display information bits at input terminal 401. The arrangement in FIG. 5 advantageously permits all decoding of the display information to be done at the source thereof, which typically may be a central processing unit. Thus, the need for decoding and selective addressing circuitry and for row and column cell drivers at the display circuit is eliminated.

Display array 500 in FIG. 5 is depicted as having n columns of k display stages each. Each display stage includes a display cell 811 and a transfer circuit 911, as indicated for display stage 511, which may be substantially similar to the display cell and transfer circuit arrangements shown in FIGS. 1 and 3. Alternating current bias voltage is extended across each display stage by source 420 over leads 421 and 422.

The individual display stages in each column are connected in tandem, with the last display stage of each column being connected to the first display stage of the succeeding column. Thus, display stage 51k of column C1 is connected to display stage 521 of column C2, for example. The input information to display array 500 on lead 431 is connected to the first display stage of the first column of the array, that is, stage 51 1 of column C1, the display image being assumed to travel from left to right in FIG. 5.

The display information received at terminal 401 is provided in blocks or columns of k display bits, successive blocks or columns of bits being separated by the time desired for the display image to be stationary between successive steps of travel of the image across the array. As a column of display bits is received at terminal 401', the bits are registered in shift register 410. Upon receipt at terminal 401 of the last bit of a column for registration in shift register 410, detector 440 provides an end-of-column signal over lead 441 to control circuit 480. Responsive thereto, control circuit 480 directs timing signals over lead 481 to shift the registered column of display bits out of shift register 410 one-bit-at-a-time to input circuit 430. The timing signals on lead 481 occur at a frequency determined by local clock 455 which advantageously may also determine the frequency of bias voltage source 420.

Input circuit 430, responsive to the first display information bit extended thereto by shift register 410, directs an appropriate write signal over lead 431 to display stage 511, turning ON display 811 if the bit is a binary one. For example, the write signal may be directed to the charge storage element of cell 811 to register a charge thereon which is sufficient in conjunction with the bias voltage from source 420 to break down the bilateral switch at cell 811 in the manner described above.

At this point then control circuit 480 provides three pulses in succession on respective leads 471, 411 and 472, in the manner of the embodiment of FIG. 1 or FIG. 3, to transfer the display bit from stage 511 to stage 512. First, a transfer pulse on lead 471 applied to the transfer circuit of each display stage effects transfer of the display information from the respective display cells to intermediate storage in the respective transfer circuits, such as from display cell 81 1 to transfer circuit 91 1 in display stage 511. Second, an erase pulse on lead 411 erases the display information from each display cell, such as in the manner of HG. 3. Finally, a transfer pulse on lead 472 to each transfer circuit effects transfer of the display information to the display cells of the succeeding display stages, such as from intermediate storage in transfer circuit 911 of stage 511 to the display cell in stage 512.

Upon completed transfer of the display bits from one display stage to the next, clear circuit 450 in control circuit 480 extends a clear signal over lead 451 in common to each display stage to discharge the intermediate storage elements in the respective stages.

Subsequently, responsive to the next timing signal over lead 481, the next display bit is shifted out of shift register 410 to input circuit 430. If the display bit corresponds to a binary one, input circuit 430 directs a corresponding write signal over path 431 to display stage 511, turning cell 811 ON. This may occur, for example, coincidentally with the appearance of the transfer pulse on lead 472, thereby registering a new display bit in stage 511 at the same time as the preceding bit is transferred to display stage 512. Thereupon, another cycle of transfer and erase pulses on leads 471, 411 and 472 effects transfer of the second display bit from stage 511 to stage 512 and, at the same time, transfer of the first display bit from stage 512 to stage 513.

The above-described operation continues until the first column of display information is shifted out of shift register 410 and is registered in display stages 511 through 51k. No further display information movement occurs until the next column of k display bits appears at terminal 401 and is registered in shift register 410, that is, until after the period of time desired for the display image to be stationary such as to pennit it to be read by an observer. When the next column of display information is registered in shift register 410 another cycle of operation takes place, transferring the previously registered column of display information from column C1 to column C2 as the new column of information is registered in column Cl. Successive columns of display information are similarly registered in the array and are transferred from column to column through the array.

In the traveling display circuit embodiments described above, the erase pulse is applied to the display cells at a time when the bias voltage across the cells is at or near zero. I have found, however, that traveling display operation is facilitated advantageously by application of the erase pulse to the cells at a time when the bias voltage is not at zero, such that a residual charge is left on the charge storage elements of the display cells that are ON, i.e., such that these display cells are only partially erased. An illustrative embodiment of a traveling display circuit in accordance with this aspect of the present invention is shown in FIG. 6 wherein display cells 600 and 620 are substantially identical to the display cells shown in the embodiment of FIG. 1, except that the bilateral switch in each cell is provided with a GATE lead. Thus, bilateral switch 612 is provided with GATE lead 631, and switch 622 with GATE lead 632.

Display information is stored in the display cells of FIG. 6 under control of control circuit 680 in the manner described above and thus circuitry therefor is not shown in FIG. 6. Further, for the purposes of description, it is assumed that erase pulses are applied in common to the individual display cells, such as in the manner shown in FIG. 1. Alternatively, a respective transistor gate may be connected to each display cell charge storage element in the manner shown in FIG. 3 for erasing the display cells. However, as mentioned above, the erase pulse in FIG. 6 is applied to the display cells at a time when the bias voltage across the cells, provided by source 650, is not at zero.

Assume, for example, that a display bit is registered in display cell 620 (i.e., that display cell 620 is ON) and that it is desired to transfer the display bit to the left to display cell 600. This is effected by applying an erase pulse to each display cell, for example, at time t in 7A and 7B, such that a residual charge, shown as voltage V, in FIG. 7B, is left on charge storage element 633 of display cell 620. The residual charge on element 633 is extended via transfer circuit 660, which illustratively comprises delay circuit 662 and diode 661, to GATE lead 631 of bilateral switch 612 in display cell 600. Subsequently, at a time advantageously near a peak of the bias voltage across display cell 600 and after the period of delay provided by circuit 662, such as at time t in FIGS. 7A and 7B, a partial write or transfer pulse is applied in common to each display cell. The transfer pulse may be applied to the display cells in the same manner as the write or erase pulses.

When a signal is applied to the GATE lead of a bilateral breakdown switch in FIG. 6, such as due to residual charge on the storage element in a preceding display cell, the breakdown voltage of the switch is lower than the normal breakdown voltage V or V lllustratively in FIG. 7A, this lower breakdown voltage is shown as V,,,. The transfer pulse applied to the display cells is insufficient, as may be seen from FIG. 7A, to break down a cell bilateral switch to a conducting state in the absence of residual charge extended thereto from the preceding display cell. Thus, the transfer pulse applied to a particular display cell, in combination with the bias voltage across the cell added to any residual charge which may be stored on the particular cell storage element, exceeds breakdown voltage V,,, but is less than breakdown voltage V or V for the switch.

Accordingly, the transfer pulse applied to display cell 600, in combination with the bias voltage across the cell and the charge extended to GATE lead 631 of bilateral switch 612 from display cell 620, breaks down switch 612 to a conducting state. The resulting current flow charges storage element 613 and energizes electroluminescent diode 616 for light-emission. Thus, by alternately applying erase and transfer pulses in common to each cell of the BEE; array at a desired traveling frequency, the display image is moved through successive cells of the array.

Although the display circuit in FIG. 6 is illustratively depicted for display image movement from right to left, it will be appreciated that left to right movement of the image can be obtained readily by connecting diode 661 and delay circuit 662between storage element 613 and GATE lead 632 of switch 622, with diode 661 poled to the right. Further, although a diode is shown illustratively in transfer circuit 660, it will be appreciated that other arrangements may be employed. For example, a pair of gating elements may be employed in transfer circuit 660, one connecting storage element 613 to GATE lead 632 of switch 622 and the other connecting storage element 633 to GATE lead 631 of switch 612, selective operation of the two gating elements providing image movement in either direction.

It is to be understood that the above-described arrangements are but illustrative of the application of the principles of my invention. Numerous other arrangements may be devised by those skilled in the art without departing from the spirit and scope of the invention.

What is claimed is:

1. A traveling display circuit comprising a plurality of display cells individually including a light-emitting element and a memory element, said memory element including charge storage means and bilateral switching means,alternating current bias means connected in common to each of said display cells, transfer circuit means connecting said display cells in tandem via said memory elements, means for registering display information in said storage means in at least one of said display cells, and pulsing means for shifting said display information through successive ones of said tandemly connected display cells, said pulsing means including means for generating shift pulses having a predetermined relationship to the output waveform of said alternating current bias means and further including means for superimposing individual ones of said pulses on said output waveform.

2. A traveling display circuit in accordance with claim 1 wherein said transfer circuit means comprises a pair of individually operable transfer elements and an intermediate storage element connected between said memory elements of adjacent ones of said tandemly connected display cells.

3. A traveling display circuit in accordance with claim 2 wherein said pulsing means comprises means for operating one of said pair of transfer elements to transfer display information from one of said adjacent connected display cells to said intermediate storage element and for thereafter operating the other of said pair of transfer elements to transfer said display information from said intermediate storage element to the other of said adjacent connected display cells.

4. A traveling display circuit in accordance with claim 3 wherein said pulsing means further comprises means for erasing display information from said memory elements of each of said display cells after the operation of said one transfer element and before the operation of said other transfer element, and means for clearing said intermediate storage elements after the operation of said other transfer element.

5. A traveling display circuit comprising a plurality of display cells individually including a light-emitting element and a memory element, said memory element including storage means and bilateral switching means; alternating current bias means connected in common to each of said display cells; transfer circuit means connecting said display cells in tandem via said memory elements, said transfer circuit means including a pair of individually operable transfer elements and an intermediate storage element; means for registering display information in said storage means in at least one of said display cells; and pulsing means operative in conjunction with said bias means for shifting said display information through successive ones of said tandemly connected display cells; said pulsing means including means for operating one of said pair of transfer elements to transfer display information from one of said adjacent connectedfiisplay cells to said intermediate storage element and for thereafter operating the other of said pair of transfer elements to transfer said display information from said intermediate storage element to the other of said adjacent connected display cells, means for erasing display information from said memory elements of each of said display cells after the operation of said one transfer element and before the operation of said other transfer element, and means for clearing said intermediate storage elements after the operation of said other transfer element; said clearing means comprising a continuously operating pulse generator including the serial combination of bilateral switching means, charge storage means and impedance means connected to said bias means, said clearing means further comprising means connecting said pulse generator in common to each of said intermediate storage elements.

6. A traveling display circuit comprising a plurality of display cells individually including a light-emitting element and a memory element, said memory element including a charge storage element and a bilateral breakdown switch, alternating current bias means connected in common to each of said display cells, transfer circuit means connecting said display cells in tandem via said memory elements, means for registering display information in said'storage element in at least one of said display cells including means operative in conjunction with said bias means to operate said bilateral breakdown switch at one of said display cells for registering a charge on said charge storage element at said one display cell, said bias means thereafter operating in conjunction with said registered charge to periodically operate said bilateral breakdown switch at said one display cell, and pulsing means operative in conjunction with said bias means for shifting said display information through successive ones of said tandemly connected display cells.

7. A traveling display circuit in accordance with claim 6 wherein said transfer circuit means comprises individual intermediate charge storage elements connected between each adjacent pair of said tandemly connected display cells.

8. A traveling display circuit in accordance with claim 7 wherein said transfer circuit means further comprises means operative with said pulsing means for transferring charge registered on said charge storage element of one of a pair of said display cells to one of said intermediate charge storage elements connected to said one display cell and for transferring charge registered on said one intermediate charge storage element to the charge storage element of the other of said pair of display cells connected to said one intermediate charge storage element.

9. A traveling display circuit in accordance with claim 8 wherein said pulsing means further COMPRISES comprises connected to each of said display cells for discharging said charge storage elements at said cells, and means connected to said transfer circuit means for discharging said intermediate charge storage elements.

10. A traveling display circuit in accordance with claim 1 wherein said transfer circuit means comprises individual delay circuit means interconnecting said memory elements of ad jacent ones of said tandemly connected display cells.

11. A traveling display circuit comprising a plurality of display cells individually including a light-emitting element and a memory element, said memory element including charge storage means and bilateral switching means, said bilateral switching means in each display cell including a bilateral breakdown switch having a gate electrode, alternating current bias means connected in common to each of said display cells, transfer circuit means connecting said display cells in tandem via said memory elements, said transfer circuit means comprising individual delay circuit means interconnecting said memory elements of adjacent ones of said tandemly connected display cells, each said delay circuit means being connected between said storage means of one display cell and said gate electrode of said bilateral breakdown switch in the immediately succeeding tandemly connected display cell, means for registering display information In said storage means In at least one of said display cells, and pulsing means operative in conjunction with said bias means for shifting said display information through successive ones of said tandemly connected display cells.

12. A traveling display circuit in accordance with claim 11 wherein said pulsing means comprises means for partially erasing display information from each of said display cells.

13. A traveling display circuit in accordance with claim 12 wherein said pulsing means further comprises means for providing a transfer signal to each of said display cells, said transfer signal being operative to store display information in a particular display cell only when the immediately preceding tandemly connected display cell contains partially erased display information registered therein. 

1. A traveling display circuit comprising a plurality of display cells individually including a light-emitting element and a memory element, said memory element including charge storage means and bilateral switching means, alternating current bias means connected in common to each of said display cells, transfer circuit means connecting said display cells in tandem via said memory elements, means for registering display information in said storage means in at least one of said display cells, and pulsing means for shifting said display information through successive ones of said tandemly connected display cells, said pulsing means including means for generating shift pulses having a predetermined relationship to the output waveform of said alternating current bias means and further including means for superimposing individual ones of said pulses on said output waveform.
 2. A traveling display circuit in accordance with claim 1 wherein said transfer circuit means comprises a pair of individually operable transfer elements and an intermediate storage element connected between said memory elements of adjacent ones of said tandemly connected display cells.
 3. A traveling display circuit in accordance with claim 2 wherein said pulsing means comprises means for operating one of said pair of transfer elements to transfer display information from one of said adjacent connected display cells to said intermediate storage element and for thereafter operating the other of said pair of transfer elements to transfer said display information from said intermediate storage element to the other of said adjacent connected display cells.
 4. A traveling display circuit in accordance with claim 3 wherein said pulsing means further comprises means for erasing display information from said memory elements of each of said display cells after the operation of said one transfer element and before the operation of said other transfer element, and means for clearing said intermediate storage elements after the operation of said other transfer element.
 5. A traveling display circuit comprising a plurality of display cells individually including a light-emitting element and a memory element, said memory element including storage means and bilateral switching means; alternating current bias means connected in common to each of said display cells; transfer circuit means connecting said display cells in tandem via said memory elements, said transfer circuit means including a pair of individually operable transfer elements and an intermediate storage element; means for registering display information in said storage means in at least one of said display cells; and pulsing means operative in conjunction with said bias means for shifting said display information through successive ones of said tandemly connected display cells; said pulsing means including means for operating one of said pair of transfer elements to transfer display information from one of Said adjacent connected display cells to said intermediate storage element and for thereafter operating the other of said pair of transfer elements to transfer said display information from said intermediate storage element to the other of said adjacent connected display cells, means for erasing display information from said memory elements of each of said display cells after the operation of said one transfer element and before the operation of said other transfer element, and means for clearing said intermediate storage elements after the operation of said other transfer element; said clearing means comprising a continuously operating pulse generator including the serial combination of bilateral switching means, charge storage means and impedance means connected to said bias means, said clearing means further comprising means connecting said pulse generator in common to each of said intermediate storage elements.
 6. A traveling display circuit comprising a plurality of display cells individually including a light-emitting element and a memory element, said memory element including a charge storage element and a bilateral breakdown switch, alternating current bias means connected in common to each of said display cells, transfer circuit means connecting said display cells in tandem via said memory elements, means for registering display information in said storage element in at least one of said display cells including means operative in conjunction with said bias means to operate said bilateral breakdown switch at one of said display cells for registering a charge on said charge storage element at said one display cell, said bias means thereafter operating in conjunction with said registered charge to periodically operate said bilateral breakdown switch at said one display cell, and pulsing means operative in conjunction with said bias means for shifting said display information through successive ones of said tandemly connected display cells.
 7. A traveling display circuit in accordance with claim 6 wherein said transfer circuit means comprises individual intermediate charge storage elements connected between each adjacent pair of said tandemly connected display cells.
 8. A traveling display circuit in accordance with claim 7 wherein said transfer circuit means further comprises means operative with said pulsing means for transferring charge registered on said charge storage element of one of a pair of said display cells to one of said intermediate charge storage elements connected to said one display cell and for transferring charge registered on said one intermediate charge storage element to the charge storage element of the other of said pair of display cells connected to said one intermediate charge storage element.
 9. A traveling display circuit in accordance with claim 8 wherein said pulsing means further COMPRISES comprises connected to each of said display cells for discharging said charge storage elements at said cells, and means connected to said transfer circuit means for discharging said intermediate charge storage elements.
 10. A traveling display circuit in accordance with claim 1 wherein said transfer circuit means comprises individual delay circuit means interconnecting said memory elements of adjacent ones of said tandemly connected display cells.
 11. A traveling display circuit comprising a plurality of display cells individually including a light-emitting element and a memory element, said memory element including charge storage means and bilateral switching means, said bilateral switching means in each display cell including a bilateral breakdown switch having a gate electrode, alternating current bias means connected in common to each of said display cells, transfer circuit means connecting said display cells in tandem via said memory elements, said transfer circuit means comprising individual delay circuit means interconnecting said memory elements of adjacent ones of said tandemly connected display cells, each said delay Circuit means being connected between said storage means of one display cell and said gate electrode of said bilateral breakdown switch in the immediately succeeding tandemly connected display cell, means for registering display information in said storage means in at least one of said display cells, and pulsing means operative in conjunction with said bias means for shifting said display information through successive ones of said tandemly connected display cells.
 12. A traveling display circuit in accordance with claim 11 wherein said pulsing means comprises means for partially erasing display information from each of said display cells.
 13. A traveling display circuit in accordance with claim 12 wherein said pulsing means further comprises means for providing a transfer signal to each of said display cells, said transfer signal being operative to store display information in a particular display cell only when the immediately preceding tandemly connected display cell contains partially erased display information registered therein. 